ITR39200 37-40 ghz 1.6 watt power amplifier mmic www.iterrac.com r3.1 sept. 15, 2004 doc. 1319 page 1 of 6 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937 fax(650) 424-1938 this is a production data sheet. se e ?product status definitions? on web site or catalog for product development status. the ITR39200 is a high efficiency power amplifier desig ned for use in point to point radio, point to multi-point communications, lmds and other millim eter wave applications. the ITR39200 is a 3- stage gaas mmic amplifie r utilizing an advanced 0.15 m gate length power phemt process and can be used in conjunction with other driver or power amplifiers to achieve the required total power output. description absolute ratings electrical characteristics (at 25c) 50 system, v d =+5 v, quiescent current (i dq ) = 1600 ma ? 19 db small signal gain (typ.) ? 32 dbm saturated power out (typ.) ? circuit contains individual source vias ? chip size 4.28 mm x 3.19 mm x 50 m features parameter symbol value unit positive dc voltage (+5 v typical) v d + 6 volts negative dc voltage v g -2 volts simultaneous (v d -v g )v dg + 8 volts positive dc current i d 2352 ma rf input power (from 50 source) p in 20 dbm operating base plate temperature t c -30 to +85 c storage temperature range t stg -55 to +125 c thermal resistance r jc 8 c/w (channel to backside) parameter min typ max unit frequency range 37 40 ghz gate supply voltage (v g ) 1 -0.2 v gain small signal (f=37-38.5 ghz) 17 19 db (f=38.5-40 ghz) 16 17 db (pin=0 dbm) gain variation vs. frequency +/-1.5 db power output at 1 db compression (f=37-38.5 ghz) 31 dbm (f=38.5-40 ghz) 30 dbm power output saturated (f=37-38.5 ghz) 31 32 dbm (f=38.5-40 ghz) 30 31 dbm (pin=+16 dbm) parameter min typ max unit drain current at pin=0 dbm 1600 ma drain current at p1db compression 1700 ma power added efficiency (pae) at p1db 17 % oip3 (17 dbm/tone) (10 mhz tone sep.) 37 dbm input return loss (pin=0 dbm) 10 db output return loss (pin=0 dbm) 10 db note: 1. typical range of the negat ive gate voltage is -0.5 to 0.0v to set a typical i dq of 1600 ma.
ITR39200 37-40 ghz 1.6 watt power amplifier mmic www.iterrac.com r3.1 sept. 15, 2004 doc. 1319 page 2 of 6 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937 fax(650) 424-1938 this is a production data sheet. se e ?product status definitions? on web site or catalog for product development status. 1.367 1.827 1.597 3.010 0.0 0.205 0.889 2.426 2.954 3.500 0.184 3.194 0.0 1.954 4.282 ground (back of chip) figure 1 functional block diagram application information rf in rf out drain supply (v da & v db ) gate supply (v ga & v gb ) mmic chip figure 2 chip layout and bond pad locations (chip size=4.282 mm x 3.194 mm x 50 m. back of chip is rf and dc ground) dimensions in mm caution: this is an esd sensitive device chip carrier material should be selected to have gaas compatible thermal coefficient of expansion and high thermal conductivity such as copper moly bdenum or copper tungsten. the chip carrier should be machined, finished flat, plated with gold over nickel and should be capable of withstanding 325c for 15 minutes. die attachment for power devices should utilize gold/tin (80/20) eutectic alloy solder and should avoid hydrogen environment for phemt devices. note that the backside of t he chip is gold plated and is used as rf and dc ground. these gaas devices should be handled with care a nd stored in dry nitrogen environment to prevent contamination of bonding surfaces . these are esd sensitive devices and should be handled with appropriate precaution including the use of wrist-grounding straps. all die attach and wire/ribbon bond equipment must be well grounded to prev ent static discharges through the device. recommended wire bonding uses 3 mils wide and 0.5 mil thick gold ribbon with lengths as short as practical allowing for appropriate stress relief. the rf input and output bonds should be typically 12 mils long corresponding to a typical 2 mil gap between the chip and the substrate material.
ITR39200 37-40 ghz 1.6 watt power amplifier mmic www.iterrac.com r3.1 sept. 15, 2004 doc. 1319 page 3 of 6 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937 fax(650) 424-1938 this is a production data sheet. se e ?product status definitions? on web site or catalog for product development status. figure 3 recommended application schematic circuit diagram drain supply (v d = +5v) (connect to both v da & v db ) gate supply (v g ) (v ga and/or v gb ) 100 pf 10,000 pf l l bond wire l?s bond wire l?s rf in rf out ground (back of chip) mmic chip 100 pf 10,000 pf l l v da (positive ) 100 pf 100 pf 100 pf 100 pf 10,000 pf 10,000 pf 10,000 pf 10,000 pf v ga (negative) v gb (negative ) v db (positive) rf input rf output 5mil thick alumina 50-ohm 5 mil thick alumina 50-ohm 2 mil gap l< 0.015? (4 plcs) die-attach 80au/20sn figure 4 recommended assembly and bonding diagram note: use 0.003? x 0.0005? gold ribbon for bonding. rf input and out put bonds should be less than 0.015? long with stress relief. vd should be biased from 1 supply on both sides as shown. vg can be biased from either or both sides from 1 supply.
ITR39200 37-40 ghz 1.6 watt power amplifier mmic www.iterrac.com r3.1 sept. 15, 2004 doc. 1319 page 4 of 6 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937 fax(650) 424-1938 this is a production data sheet. se e ?product status definitions? on web site or catalog for product development status. caution: loss of gate voltage (v g ) while drain voltage (v d ) is present may damage the amplifier chip. the following sequence of steps must be fo llowed to properly test the amplifier: recommended procedure for biasing and operation step 1: turn off rf input power. step 2: connect the dc supply grounds to the ground of the chip carrier. slowly apply negative gate bias supply voltage of -1.5 v to v g . step 3: slowly apply positive drain bias supply voltage of +5 v to v d . step 4: adjust gate bias voltage to set the quiescent current of i dq =1600 ma. note: an example of an auto bias sequencing circuit to apply negativ e gate voltage and positive drain voltage for the above procedure is shown below. step 5: after the bias condition is established, the rf input signal may now be applied at the appropriate frequency band. step 6: follow turn-off sequence of: (i) turn off rf input power. (ii) turn down and off drain voltage (v d ). (iii) turn down and off gate bias voltage (v g ). application information auto-bias circuit mmic_+v da or v db mmic_+v da or v db
ITR39200 37-40 ghz 1.6 watt power amplifier mmic www.iterrac.com r3.1 sept. 15, 2004 doc. 1319 page 5 of 6 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937 fax(650) 424-1938 this is a production data sheet. se e ?product status definitions? on web site or catalog for product development status. -5 0 5 10 15 20 25 34 35 36 37 38 39 40 41 42 frequency ( ghz) gai n ( db) -30 -20 -10 0 10 20 30 re turn lo s s (db) performance data 10 15 20 25 30 35 36 37 38 39 40 frequency ( ghz) output power ( dbm) large signal gain p1d b ITR39200 s-parameters vs. frequency bias v d =5 v, i dq =1600 ma, t=25 c ITR39200 power and ls gain @ p1db vs. frequency bias v d =5 v, i dq =1600 ma, t=25 c
ITR39200 37-40 ghz 1.6 watt power amplifier mmic www.iterrac.com r3.1 sept. 15, 2004 doc. 1319 page 6 of 6 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937 fax(650) 424-1938 this is a production data sheet. se e ?product status definitions? on web site or catalog for product development status. ITR39200 oip3 vs. pout/tone v d =5v i dq =1600ma t=25c 10 mhz tone sep 34 35 36 37 38 39 40 41 4 6 8 101214161820222426283032 pout/tone (dbm) oip3l (dbm) 37 ghz 38 ghz 39 ghz 40 ghz 14 15 16 17 18 19 20 21 22 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 pout (dbm) gain (db) 37ghz 38ghz 39ghz 40ghz ITR39200 gain vs. power out frequency= 37 to 40 ghz, bias v d =5 v, i dq =1600 ma, t=25 c performance data
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